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IDT74ALVCH162827 3.3V CMOS 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS AND BUS-HOLD
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 20-BIT BUFFER/ DRIVER WITH 3-STATE OUTPUTS AND BUS-HOLD
FEATURES:
* 0.5 MICRON CMOS Technology * Typical tSK(o) (Output Skew) < 250ps * ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) * VCC = 3.3V 0.3V, Normal Range * VCC = 2.7V to 3.6V, Extended Range * VCC = 2.5V 0.2V * CMOS power levels (0.4 W typ. static) * Rail-to-Rail output swing for increased noise margin * Available in SSOP, TSSOP, and TVSOP packages
IDT74ALVCH162827
DESCRIPTION:
This 20-bit buffer/driver is built using advanced dual metal CMOS technology. The ALVCH162827 device provides high-performance bus interface buffering for wide data/address paths or busses carrying parity. Two pairs of NAND-ed output enable controls offer maximum control flexibility and are organized to operate the device as two 10-bit buffers or one 20-bit buffer. Flow-through organization of signal pins facilitates ease of layout. All inputs are designed with hysteresis for improved noise margin. The ALVCH162827 has series resistors in the device output structure which will significantly reduce line noise when used with light loads. This driver has been designed to drive 12mA at the designated threshold levels. The ALVCH162827 has "bus-hold" which retains the inputs' last state whenever the input bus goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors.
DRIVE FEATURES:
* Balanced Output Drivers: 12mA * Low switching noise
APPLICATIONS:
* 3.3V high speed systems * 3.3V and lower voltage computing systems
FUNCTIONAL BLOCK DIAGRAM
1O E1 1O E2
1 56
2O E1 2O E2
28 29
1A 1
55
2
1Y 1
2A 1
42
15
2Y 1
TO NINE OTHER CHANNELS
TO NINE OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
(c)1999 Integrated Device Technology, Inc.
MARCH 1999
DSC-4567/2
IDT74ALVCH162827 3.3V CMOS 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS AND BUS-HOLD
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
1O E1 1Y 1 1Y 2
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM(2) Description Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature DC Output Current Continuous Clamp Current, VI < 0 or VI > VCC Continuous Clamp Current, VO < 0 Continuous Current through each VCC or GND Max -0.5 to +4.6 -0.5 to VCC+0.5 -65 to +150 -50 to +50 50 -50 100 Unit V V C mA mA mA mA
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
1O E2 1A 1 1A 2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
VTERM(3) TSTG IOUT IIK IOK ICC ISS
GND
1Y 3 1Y 4
GND
1A 3 1A 4
VCC
1Y 5 1Y 6 1Y 7
VCC
1A 5 1A 6 1A 7
GND
1Y 8 1Y 9 1Y 10 2Y 1 2Y 2 2Y 3
GND
1A 8 1A 9 1A 10 2A 1 2A 2 2A 3
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC.
CAPACITANCE (TA = +25C, F = 1.0MHz)
Symbol CIN COUT COUT Parameter(1) Input Capacitance Output Capacitance I/O Port Capacitance Conditions VIN = 0V VOUT = 0V VIN = 0V Typ. 5 7 7 Max. 7 9 9 Unit pF pF pF
NOTE: 1. As applicable to the device type.
GND
2Y 4 2Y 5 2Y 6
GND
2A 4 2A 5 2A 6
PIN DESCRIPTION
Pin Names xOEx xAx xYx Description Output Enable Inputs (Active LOW) Data Inputs(1) 3-State Outputs
VCC
2Y 7 2Y 8
VCC
2A 7 2A 8
NOTE: 1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
GND
2Y 9 2Y 10 2O E1
GND
2A 9 2A 10 2O E2
FUNCTION TABLE (EACH 10-BIT SECTION)(1)
Inputs xOE1 xOE2 L L X H xAx L H X X L L H X Output xYx L H Z Z
SSOP/ TSSOP/ TVSOP TOP VIEW
NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High Impedance
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IDT74ALVCH162827 3.3V CMOS 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS AND BUS-HOLD
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = -40C to +85C
Symbol VIH Parameter Input HIGH Voltage Level VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VIL IIH IIL IOZH IOZL VIK VH ICCL ICCH ICCZ ICC Input LOW Voltage Level Input HIGH Current Input LOW Current High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = 2.3V, IIN = -18mA VCC = 3.3V VCC = 3.6V VIN = GND or VCC One input at VCC - 0.6V, other inputs at VCC or GND VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V VCC = 3.6V VCC = 3.6V VI = VCC VI = GND VO = VCC VO = GND Test Conditions Min. 1.7 2 -- -- -- -- -- -- -- -- -- Typ.(1) -- -- -- -- -- -- -- -- -0.7 100 0.1 Max. -- -- 0.7 0.8 5 5 10 10 -1.2 -- 40 V mV A A A A V Unit V
Quiescent Power Supply Current Variation
--
--
750
A
NOTE: 1. Typical values are at VCC = 3.3V, +25C ambient.
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO
NOTES: 1. Pins with Bus-Hold are identified in the pin description. 2. Typical values are at VCC = 3.3V, +25C ambient.
Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current VCC = 3V VCC = 2.3V VCC = 3.6V
Test Conditions VI = 2V VI = 0.8V VI = 1.7V VI = 0.7V VI = 0 to 3.6V
Min. - 75 75 - 45 45 --
Typ.(2) -- -- -- -- --
Max. -- -- -- -- 500
Unit A A A
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IDT74ALVCH162827 3.3V CMOS 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS AND BUS-HOLD
INDUSTRIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol VOH Parameter Output HIGH Voltage VCC = 2.3V VCC = 2.7V VCC = 3V VOL Output LOW Voltage VCC = 2.3V to 3.6V VCC = 2.3V VCC = 2.7V VCC = 3V Test Conditions(1) VCC = 2.3V to 3.6V IOH = - 0.1mA IOH = - 4mA IOH = - 6mA IOH = - 4mA IOH = - 8mA IOH = - 6mA IOH = - 12mA IOL = 0.1mA IOL = 4mA IOL = 6mA IOL = 4mA IOL = 8mA IOL = 6mA IOL = 12mA Min. VCC - 0.2 1.9 1.7 2.2 2 2.4 2 -- -- -- -- -- -- -- Max. -- -- -- -- -- -- -- 0.2 0.4 0.55 0.4 0.6 0.55 0.8 V Unit V
NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = - 40C to + 85C.
OPERATING CHARACTERISTICS, TA = 25C
VCC = 2.5V 0.2V Symbol CPD CPD Parameter Power Dissipation Capacitance Outputs enabled Power Dissipation Capacitance Outputs disabled Test Conditions CL = 0pF, f = 10Mhz Typical 16 4 VCC = 3.3V 0.3V Typical 18 6 Unit pF
SWITCHING CHARACTERISTICS(1)
VCC = 2.5V 0.2V Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ tSK(O) Parameter Propagation Delay xAx to xYx Output Enable Time xOEx to xYx Output Disable Time xOEx to xYx Output Skew(2) -- -- -- -- -- 500 ps 1.7 5.9 -- 5.2 1.8 4.7 ns 1.4 6.3 -- 6.2 1.6 5.1 ns Min. 1 Max. 4.4 VCC = 2.7V Min. -- Max. 4.4 VCC = 3.3V 0.3V Min. 1.5 Max. 3.8 Unit ns
NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = - 40C to + 85C. 2 Skew between any two outputs of the same package and switching in the same direction.
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IDT74ALVCH162827 3.3V CMOS 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS AND BUS-HOLD
INDUSTRIAL TEMPERATURE RANGE
VIH VT 0V VOH VT VOL VIH VT 0V
ALVC Link
TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS
Symbol VLOAD VIH VT VLZ VHZ CL VCC(1)= 3.3V0.3V VCC(1)= 2.7V 6 2.7 1.5 300 300 50
VCC 500 Pulse Generator
(1, 2)
SAME PHASE INPUT TRANSITION
VCC(2)= 2.5V0.2V 2 x Vcc Vcc Vcc / 2 150 150 30
Unit V V V mV mV pF
VLOAD Open GND
tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION
tPHL
6 2.7 1.5 300 300 50
tPHL
Propagation Delay
ENABLE CONTROL INPUT tPZL OUTPUT SW ITCH NORMALLY CLOSED LOW tPZH OUTPUT SW ITCH NORMALLY OPEN HIGH VLOAD/2 VT tPHZ VT 0V tPLZ DISABLE VIH VT 0V VLOAD/2 VLZ VOL VOH VHZ 0V
ALVC Link
VIN D.U.T.
VOUT
RT
500 CL
ALVC Link
Test Circuit for All Outputs
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns. 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2ns; tR 2ns.
Enable and Disable Times
NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. VIH DATA VT INPUT 0V tSU tH VIH TIMING VT INPUT 0V tREM VIH ASYNCHRONOUS VT CONTROL 0V VIH SYNCHRONOUS VT CONTROL tSU 0V tH
ALVC Link
SWITCH POSITION
Test Open Drain Disable Low Enable Low Disable High Enable High All Other Tests Switch VLOAD GND Open
VIH INPUT VT 0V VOH OUTPUT 1 VT VOL VOH OUTPUT 2 tPLH2 tPHL2
ALVC Link
Set-up, Hold, and Release Times
tPLH1
tPHL1
LOW-HIGH-LOW PULSE tW HIGH-LOW -HIGH PULSE
VT
tSK (x)
tSK (x)
VT VOL
VT
ALVC Link
Pulse Width
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
Output Skew - tSK(X)
NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
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IDT74ALVCH162827 3.3V CMOS 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS AND BUS-HOLD
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT XX ALVC X XXX Fam ily XXX Device Type XX Package Tem p. R ange Bus-Hold
PV PA PF 827 162
Shrink Sm all O u tline Package Thin Shrink Sm all O utline Packa ge Thin Very Sm all O utline Package 20-Bit Buffer/Driver with 3-State O utputs Double-D ensity with Resistors, 12m A
H 74
Bus-Hold - 40C to +85C
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